Enginursday: Innovative Testbed Design (Part 1 of 2)

Hey Tone! I was hoping you'd find this post! You definitely deserve all the credit for an awesome name. It was kind of random, but I remember thinking, "Why not name this after my favorite AVC teamname?" I have always been stoked on the team names at AVC, but yours really stuck out for me, cause of my slight obsession with flying RC planes (and good salsa). But I do remember seriously considering "Daisy Rover" and "Lawn Dart". Can you remember any other good ones?

When I tell people about the history of this name, it always brings a smile to learn about a team of engineers designing an autonomous flying robot named the Flying Jalapeno. And your logo was so great and hilarious. And I also love people throwing it around with a straight face when we are talking "serious business" about the code library or any future testbed designs. Sadly, it has also been commonly referred to as just "FJ". Doesn't have the same effect :)

Also, I thought you might enjoy knowing that your name has inspired future testing tool names as well. One of our test developers is currently working on the Flying Serrano (a smaller 328 based version).

Hey 773, Another good point, for sure. I usually like to keep the serial debug header PTH, and actually opt to use PTH connectors on most testbeds. But with this design, I opted to decrease the time spent at the Selective Solder Machine. Production was already gonna have to SS the big 2x30, the Mosfets and the Barrel Jack. (which by the way, I always go with PTH barrel jacks - that has been a bit of a challenge on our Redboard, because AOI has trouble seeing the very slight "pillow style" cold joints.

The good news is that we haven't seen a single SMD 1x6 header be damaged on a Flying Jalapeno yet, so everyone is being careful enough. The other thing we have going for us here, is that it is usually only inserted once during setup and then left alone for the duration of testing a single batch. I did opt to keep in positioned in the design so that the headers are not overhanging the edge of the PCB. We've had plenty of testbeds with overhang pin connectors, and they always end up getting bend during handling or placement in the bin, and sometimes even cracked off.

As always, thanks for your feedback!

Hey Steve, Thanks for checking this out! All valid points, but still not the one I'm thinking of.

Via tenting is an age old issue around here. We are always checking the eagle files and gerbers before ordering to ensure their covered. The Eagle DRC can actually open them up (even if you don't want it too), so always make sure to view the "tStop" and "bStop" layers before CAMming up your gerbers.

These vias on the Flying Jalapeno are definitely tented full in the gerbers, but our fab house, Gold Pheonix, has decided to pull back the silk a bit around drill hits. The mask is really the most important thing, and they did allow that to cover them up. But the other thing that's going on here is that, usually once you get up to 20 mil via drill hits or bigger, the mask can't actually fill the drill hit, so it looks uncovered. Sometimes, even though the mask was manufactured over the edge of the drill hit, it will still expose the edge and there is a little tiny ring of metal exposed. I probably should have just gone with 15 mil via hits, those usually look better, and have sufficient plating for any of my current needs (which is barely anything on most data IO lines).

If you look at a more recent board like the Qwiic Twist, you can see that these 12 mil vias are fully covered in mask (most of the time), and silk can print over them pretty nicely. Although, I will say, we do our best to avoid silk over vias on all storefront designs.

And good catch on the mosfets not having room for heatsinks. I definitely overlooked this, but luckily, we haven't needed them on any testbed designs so far. Most of our products require such minimal current, that these mosfets stay cool as is.

Thanks!

Hey 403, Thanks for looking! Indeed PTH is always stronger and usually the way to go for test jigs. The SMD choice here was intentional to save assembly time. More details at this comment here. Thanks!

Hey John, Good catch, but sorry, not the one. I totally didn't even think of heat sinks while designing this, or after using it so many times. Whoops! I guess we just have pretty minimal power requirements for most of our products and so these power circuits are pretty overkill (even without heat sinks).

The only testbed that ever used heat sinks (that I can remember) was for our Stepoko motor driver. I usually share that one on Friday tours because it's enormous and has some cool acto-botics parts with swinging arms, magnets and reed switches. The entire test apparatus I think is about 10"x15" inches (a full QC testbed PCB Panel) and has some seriously beefy traces and stepper motors.

About them getting whacked loose. A valid concern. They do occasionally get bend over and touch the nearby housing of the capacitors, but I haven't seen this cause a problem or crack off yet.

I will say... the error I'm thinking of does not involve a physical weakness, unless, I guess you are thinking that the microscopic internal movement of particles inside transistors being weak in some specific instance.

Thanks!!

Hey Madbodger, Thanks for commenting! What do you mean by strapping? I'm guessing, like a jumper option? If so, that's an interesting improvement. Currently the logic level conversion (on the serial UART lines) is matching the ATMega2560's logic level. This is not the error/feature I was thinking of... but I will say... thinking about logic level is getting warm.

Thanks!!

Hey jma89, Good guess. Thanks for looking at my design! I can see how it looks that way in the picture. Although there are some slightly isolated ground pours, the bottom copper is a pretty solid return path (thru the GND pins on the 2x30 connector). On the next revision, I will take your observation here into account and ensure the top ground pour has improved return paths on the top copper as well.

To be fair, this would be much easier to see with the design files and/or a picture of the bottom (so I definitely commend you for seeing this with only a top down picture). I plan to release all the eagle files and a few more pictures at the next post, so all will become clear, I promise. Thanks again!

Hey Haathi, Thanks for commenting! Good eye for sure. But sorry, that isn't the design flaw I'm looking for. It isn't an actual assembly error (or design flaw that is causing an assembly error).

You are correct though, that is a less than ideal solder connection on that bottom left GND pin. It's pretty hard to tell, but that dark spot is, in fact, the shadows down into that PTH drill hit. This means that the solder did not actually flow up through the header and so did not form a good fillet on the top side. This is probably due to the fact that I opted to make that GND pour flow "thru" that PTH pad (without the usual isolate and thermal tick marks - known as "thermals" in Eagle). I did this to ensure I could have a really good connection from the pin to the GND pour. Well, that didn't really work that well :) But luckily, We do get really good fillets on the bottom side of this connector.

We use our selective solder machine to solder these parts into this PCB, and so I'm wondering if we could increase the flux spray on that pin and/or decrease the run speed. I'll have to check in with our equipment operators to see if these are potential solutions. But my gut is telling me that I probably should have opted for thermals and the 8 tick marks should provide plenty of connection for most current demands. This is a habit I have for most hand assembled test fixtures, because I'm happy to spend a little extra time with my iron (and add extra flux if necessary) to get good fillets on any non-thermalled PTH pad.

Thanks!

That might be just a bad picture/angle. There are several pins that have that same dark spot that looks like a hole where there should be solder.

Hey 773, Thanks for checking this out! I knew I could count on you for a good testbed review :) And good catches for sure. Although, sorry to say, they are not the one I'm thinking of.

I hope it's not too hard to see from the pic. I'm not sure if I should give any clues, but I thought I'd see how the response goes for at least a couple days before giving any. I will say that you and dksmall are getting warmer, and that all of the values do match the actual parts on the board...

Good catch on the LED below the "POWER" silk. I assumed (never a good idea), that the "POWER" silk was clearly labeling the LED, but in fact it could be labeling the barrel jack connector.

Good catch on the capacitor north of the ATMega2560 IC. It is in fact a 0.1uF cap, and I, whoops, missed labeling that for sure. I should at least stay consistent within my own strange habits!!!

Good catch on the 2x3 socket on the right side of the board. That is a programming port. We use this primarily for programming the arduino bootloader onto the ATMega2560. I suppose we do normally put an "ISP" silk label next to these style programming headers (on storefront products. I guess I overlooked it because I'm so used to any 2x3 (on an AVR based design) always being used for this purpose. Also, the "pin 1" marking kind of indicates that it's for something more important than just 6 random GPIOs (but I could be overthinking here). Either way, I will make sure to add in clear silk label on the revision.

Funny you should mention the larger sparkfun logo. I'll admit, I didn't think too much about the aesthetics of this design. I'm not sure my first round of protos even had an SFE logo on them at all. We don't usually put an SFE Logo on testbed designs. It's funny though, once I did add them, I put a giant one on the bottom side. It spans the entire width of the PCB!!

Thanks 773!!

Hey 773, Thanks for sharing! Indeed, it sure is nice to have field-replaceable parts on wear-n-tear testing equipment. We probably replace USB cables on test fixtures more often than any other parts. We are hoping that the recent shift to USB C will be more rugged. MicroBs always die after so long in production. I have found myself troubleshooting many other things first, and then I go "durp, is the USB cable bad?".

We once designed a custom breakout board to make a replaceable "DIP" socket connector for the Edison Block products. They had a nasty little fine-pitched connector that would never last beyond a few hundred insertions.

PS we still use Gold Phoenix as our primary production quantity fab house. Only recently, I noticed that they have a pool service for getting onto a "pool" and ordering small quantity orders. Looks kind of like the same business model as OSH Park. Could be good. Although, we are big fans of OSH Park around here. They do good stuff, and it sure is easy to make an order.

Wow! Your test controller board sounds rad! I would love to see a pic. I just checked in with our IT team, and we decided to not allow picture uploads to comments due to the overwhelming amount of spam-bots around these days. I wonder if you could post it elsewhere (like gdrive or dropbox) and share a public link?

Also, I was under the impression that flying probe machines were very expensive. I once went to the IPC Expo in San Diego (like 2012ish I think), and we saw some really impressive machines (pretty fun to watch), but they were 200K+. Have they come down in price or are there cheaper options now?

Thanks for checking this out dksmall! Sorry, but those part values in the silk are intentional. I can definitely understand how that would look like a flaw and is not the best standard design practice. It's an unusual habit that I am fully to blame for on testbed design. We build them all by hand with an iron, and we have a rather small parts inventory that is specifically for testbed parts, and so it's really nice to build up a test jig without having to look up a BOM or reference the design files. It does become confusing, though, when you ultimately find out that your testbed design needs a different value then planned. I'll admit, there are a few mistakes fixed with a sharpie out in production.

Part reference designators on the silk have been omitted from SparkFun storefront products since the very beginning, so I guess we have Nathan to blame for that :) But actually, I do agree with our belief that labeling the connection points always should take priority, and sometimes it's nice to gain that space. Some designs would have to increase in size to make room for the designator silk, and just wouldn't be justified when the product's small size is it's key feature (I'm thinking about the Pro mini or the OpenLog).

Thanks BricoGeek, and nice catch about the via clearance issue. But sorry, that was not the error I am looking for. Now I'm wondering how many other errors people are gonna catch - I hope a ton! Well not really, but I'm always glad to hear feedback and any improvement ideas.

You are definitely right though, that via is a little too close to that screw terminal. We try to avoid routing traces or having any vias under screw heads on storefront designs. I guess I was a little lenient on the rules here, being an in-house tool. But with a some more effort (and some help from Eagle 9), I bet we could easily make more room and scoot that away on the next revision.

I expect that I speak not only for myself, but for many (all?) of the Blog readers, when I wish you, and everyone at SparkFun, happy holidays, and that most of us are looking forward to reading Part 2!