So are you saying that if you want to start learning FPGA (from somebody who only knows standard logic) that you should get this board AND this Hamster's LogicWing? Got a link for Hamster's LogicWing? Thanks

Is there some reason you have to use VHDL if you're outside the US?

The reason there are only 48 I/O lines available for use is due to the fact that the chip is in a CP132/CPG132 package. This package allows only 92 IO lines, many of which are most likely reserved for interfacing through the FTDI and any other additional resources the board has on it.

Never tried it, but I'd imagine it would work. You may have slight compatibility issues however

I was able to fasten my standoffs to a flat surface that prevents my board from tipping over (I basically crazy glued the posts to a flat, thin sheet of plastic) and everything is fine. This is by far the easiest FPGA platform I've worked with and I've worked with Xilinx (Spartan 3E), Lattice (MachXO dev board which is marketed as a CPLD but it's really a FPGA in CPLD clothing), and Altera (DE0 Nano). The helper scrips and pin assignment file are crucial to a successful synthesis. This is a GREAT package for beginners and experts alike.

Here's my trick - get four 40 pin header strips (code PRT-00116) and use them to hold all the headers in place while you solder them. You could get away with one or two strips, but with four you can hold all the headers in place at the same time.

Your headers will be perfectly aligned and you can then use the pins to attack your projects to the Papilio.

I don't find these hard to solder at all. Consider them good easy practice :) I've never messed this kind of job up and I'm terrible at soldering

As sgrace replied, you would use the DCM. On the Papilio site there is a video tutorial on how to use the DCM. I suggest checking that out to get your head around clocks.

I also wanted to add, you definitely DON'T want to be creating your own clock manager or PLL. PLL's are very non-digital (they live primarily in analog land) and are very difficult to synthesize correctly. If you can't use DCM or a PLL, the best bet is to use clock enables. That way you clock your entire design with the same 32Mhz clock so there should be no skew. The clock enables enable operation on rising edge of the clock signal and prevents timing errors in your design.

FPGAs do not have internal clocks, and you have to give the FPGA a clock frequency to work with. IN this case, they are providing a 32MHz frequency to use. From here you can use features of the FPGA like a Digital Clock Manager (DCM) to adjust the clock to something more specific for your needs.

Consult documentation. In a case like this you would need to look at the Spartan-3 HDL Design Guide.

FPGAs don't have preset clock frequencies. Their speed depends on various propagation times as well as the precision required by the code they're running. That said, the P1 has a 32MHz oscillator that you can use as a reference for slower or faster clocks in your circuit.

You're missing the fact that this is targeted at beginners and non EE types. You don't jump through anything. I don't own one but I do own a small Altera board from knjn.com and it works in a similar manner, though its just plain old rs232. You use a vendor supplied program to upload the bit stream to the boot ROM. You cant debug but there is a jtag header so you can still program/debug it strait from ISE if you wanted.

Bottom line is this is like the Arduino, a low cost introduction platform. You are not its intended audience.

The breakout board doesn't have PROM to program the bitstream to for your FPGA to be persistent.

From there site:

The JTAG programming port is included for use with external JTAG programmers such as the Xilinx JTAG cables. The Xilinx tools such as Impact and the EDK do not support FT2232D based programmers nor does Xilinx provide any method to add support for non-Xilinx programmers.

I don't think it's necessarily a limitation unless you are wanting to do some Chipscope type debugging.

250k FPGAs are on their way out, and this is VERY cheap for a 500k. Look at SFE's development board which is 100 bucks!

I am not going to deny that there are good open sourced compilers/debuggers/simulators and do what they can, but the BEST software out there always has a steep learning curve. But did you know that a lot of that stuff is based off the industry software like the Xilinx ISE Tools? I have tried Icarus for HDL in college, but it was cumbersome to install and use. It's MUCH easier to suck-up the 8GB install and use tools that are designed and tested on Linux AND Windows (sorry Mac users). Just remember the industry software is for professionals, not hobbyists. Besides, Xilinx provides tutorials for their software AND they have a Documentation Navigator that has EVERY SPECIFICATION DOCUMENT THEY PRODUCE!

FPGA development is very difficult to someone who has not had been classically trained (courses/colleges). By using an industry software that provides a FREE version for people to use makes things easier. Their support forums are great with a lot of contributors. The other thing is, FPGA stuff is not cheap, period.

I recommend to new users to suck up and buy a reference book to use. I recommend this one: http://www.amazon.com/Digital-Design-Edition-Morris-Mano/dp/0131989243/ref=ntt_at_ep_dpt_3

I find Mano's style of writing to be perfect for someone who has never done digital logic before (I still reference him in my designs). Yes the book is expensive, but worth it's weight in gold if you do FPGA development.

There is also another nice program for developing both Verilog and VHDL code call Active HDL by Aldec. Its a professional tool but they do offer a free (but limited) student edition that does not require student verification. Just sign up for the free student edition and you get a download link via email. Its windows only though :-( http://www.aldec.com/en/products/fpga_simulation/active-hdl

But I agree ISE is a visual mess, the interface is clumsy. I always felt more comfortable in Quartus II. There should be more low cost Altera devices on the market.